The present invention relates generally to circuits. More particularly, it relates to a high-speed logic gate, such as an xe2x80x98ORxe2x80x99 gate, having improved switching performance and which may be used in various applications such as a prescaler for a frequency synthesizer.
Logic gates are commonly used to implement various logic functions. For example, OR gates may be used in conjunction with flip-flops to implement a dual modulus divider capable of dividing an oscillator signal by one of a number of divide factors (e.g., four and five). An example design of such dual modulus divider is described herein. For some applications (e.g., wireless, networking, and so on), the oscillator signal may be a radio frequency (RF) signal. The dual modulus divider is typically the fast operating logic, and may be required to operate based on the RF signal. In this case, if the dual modulus divider can be designed to operate faster, a higher oscillator frequency may be supported and new applications may be possible.
To increase the operating speed of the synchronous circuits such as the dual modulus divider, it is necessary to reduce the propagation delay of logic gates between synchronous elements. If a logic gate is inserted between stages of flip-flops, or implemented in feedback loops, additional delay is introduced which then limits the speed at which the flip-flops may be clocked.
As can be seen, high-speed logic gates, such as OR gate, having improved switching performance are highly desirable. These gates may be advantageous used for various high-speed logics such as a prescaler and other circuits required to operate at a high clock frequency.
The invention provides techniques to improve the operating speed and switching performance of a logic gate. Via the use of a (positive) feedback circuit, various improvements in performance may be obtained such as (1) faster signal swing on the output signal, (2) stronger output signal drive, (3) improved noise margin, and so on. The feedback circuit may be used to implement high-speed logic based on, for example, current-mode logic (CML). The improvements provided by the feedback circuit are especially advantageous for logic implemented in complementary metal oxide semiconductor (CMOS), which is inherently a slower process than some other processes such as bipolar and bipolar-CMOS.
An embodiment of the invention provides a logic gate that includes a first differential amplifier and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses input signals applied to the non-inverting inputs, and provides a differential output that is a particular logic function (e.g., an xe2x80x98ORxe2x80x99) of the input signals. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form an OR function. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The logic gate typically further includes a second differential amplifier that senses and further drives the differential output.
The feedback circuit can provide positive feedback between the output of the logic gate and the inverting input of the first differential amplifier. This feedback may provide various improvements in the signal characteristics. The control signal can dynamically adjust the inverting input of the first differential amplifier to provide improved switching performance. This dynamic adjustment can be achieved by driving the inverting input to a polarity that is opposite from an OR of the input signals applied to the non-inverting inputs.
The feedback circuit can be implemented with a third differential amplifier comprised of a pair of transistors having sources that couple together. One transistor has a gate that couples to the non-inverting output of the logic gate and a drain that couples to the inverting input of the first differential amplifier. The other transistor has a gate that can couple to a bias voltage, VB, or to the inverting output of the logic gate, and a drain that can couple to a resistive or active load or VCC.
Various other aspects, embodiments, and features of the invention are also provided, as described in further detail below.